Virtex®-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardwarecomponents to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL™(Advanced Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct sub-families. This overviewcovers the devices in the LXT, SXT, and HXT sub-families. Each sub-family contains a different ratio of features to most efficiently addressthe needs of a wide variety of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many builtin system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGAbased systems. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 FPGAs are a programmable alternative to customASIC technology. Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performanceDSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and softmicroprocessor capabilities.Features• Three sub-families:• Virtex-6 LXT FPGAs: High-performance logic withadvanced serial connectivity• Virtex-6 SXT FPGAs: Highest signal processingcapability with advanced serial connectivity• Virtex-6 HXT FPGAs: Highest bandwidth serialconnectivity• Compatibility across sub-families• LXT and SXT devices are footprint compatible inthe same package• Advanced, high-performance FPGA Logic• Real 6-input look-up table (LUT) technology• Dual LUT5 (5-input LUT) option• LUT/dual flip-flop pair for applications requiring richregister mix• Improved routing efficiency• 64-bit (or two 32-bit) distributed LUT RAM optionper 6-input LUT• SRL32/dual SRL16 with registered outputs option• Powerful mixed-mode clock managers (MMCM)• MMCM blocks provide zero-delay buffering,frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division• 36-Kb block RAM/FIFOs• Dual-port RAM blocks• Programmable– Dual-port widths up to 36 bits– Simple dual-port widths up to 72 bits• Enhanced programmable FIFO logic• Built-in optional error-correction circuitry• Optionally use each block as two independent18 Kb blocks• High-performance parallel SelectIO™ technology• 1.2 to 2.5V I/O operation• Source-synchronous interfacing usingChipSync™ technology• Digitally controlled impedance (DCI) activetermination• Flexible fine-grained I/O banking• High-speed memory interface support withintegrated write-leveling capability• Advanced DSP48E1 slices• 25 x 18, two’s complement multiplier/accumulator• Optional pipelining• New optional pre-adder to assist filteringapplications• Optional bitwise logic functionality• Dedicated cascade connections• Flexible configuration options• SPI and Parallel Flash interface• Multi-bitstream support with dedicated fallbackreconfiguration logic• Automatic bus width detection• System Monitor capability on all devices• On-chip/off-chip thermal and supply voltagemonitoring• JTAG access to all monitored quantities• Integrated interface blocks for PCI Express® designs• Compliant to the PCI Express Base Specification2.0• Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support withGTX transceivers• Endpoint and Root Port capable• x1, x2, x4, or x8 lane support per block• GTX transceivers: up to 6.6 Gb/s• Data rates below 480 Mb/s supported byoversampling in FPGA logic.• GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s• Integrated 10/100/1000 Mb/s Ethernet MAC block• Supports 1000BASE-X PCS/PMA and SGMIIusing GTX transceivers• Supports MII, GMII, and RGMII using SelectIOtechnology resources• 2500Mb/s support available• 40 nm copper CMOS process technology• 1.0V core voltage (-1, -2, -3 speed grades only)• Lower-power 0.9V core voltage option (-1L speedgrade only)• High signal-integrity flip-chip packaging available instandard or Pb-free package options